1. Field of the Invention
The invention relates to analog to digital converters, namely electronic circuits capable of converting an analog input signal into a precise digital value representing the amplitude of the analog signal. The digital value is obtained in the form of a word of several bits, generally encoded in pure binary form.
There are several existing methods of conversion, and the choice of one method rather than another depends on the performance characteristics required from the converter. Of these performance characteristics, the most important parameters are the following
the resolution, defined by the number of bits of the output word providing an exact representation of the amplitude of the analog signal; the number of bits may range from 16 to 18, or even 20 for converters with the highest precision, and the precision is generally + or -1/2 least significant bit; PA1 the speed, namely the number of conversion operations that can be performed in one second; PA1 the power consumption: a fast and precise converter consumes far more energy than a slow, low-precision converter; now, the power consumption gives rise to a heating of the integrated circuit chip on which the converter is made. This heating must be compensated for by cooling means that make it difficult to use the circuit when there are constraints of space availability to be met. Furthermore, with the increasing number of so-called "portable" devices (namely devices working with batteries), the criterion of&lt;&lt;high power consumption&gt;&gt;is becomong synonymous also with the&lt;&lt;short lifetime of equipment&gt;&gt;; PA1 and of course there is the cost of designing and manufacturing the converter related especially to the surface area of the integrated circuit chip used by the converter. PA1 successive approximation converters which compare the input analog signal Vin successively with digital values, each time approaching the value of the analog signal a little more closely; these converters work in at least N phases if the value is encoded on N bits; they are generally very slow for values of precision exceeding 6 or 8 bits; PA1 "flash" converters which use 2.sup.N parallel-connected comparators; the comparators each receive firstly the analog signal and secondly one of the 2.sup.N reference voltages defined by a bridge of 2.sup.N precision resistors; these converters are very fast (with generally two phases) but they are very bulky and consume a very great deal of power when the value of N reaches 10 to 12 bits; PA1 combined converters having one coarse converter to obtain most significant bits and one fine converter to obtain least significant bits; the coarse converters may be fast, low-precision converters (with precision values of 4 to 6 bits for example); the fine converter must be precise even if it is slower. PA1 three pairs of inputs receiving, as input signals, three pairs of output signals from a k-1 order interpolation and selection circuit, the signals of a pair having equal values when the voltage to be converted Vin is equal to one of the three k-1 order main reference voltages, these three voltages mutually defining an interval consisting of two k-1 order voltage half-intervals, PA1 means for the setting up, from the input signals, of five pairs of signals known as interpolation signals, each pair comprising two interpolation signals that vary symmetrically and monotonically as a function of the voltage Vin, the signals of one pair being equal when the voltage Vin is equal to a reference voltage associated with this pair, the five reference voltages associated with the five pairs being substantially, firstly, the three k-1 order main reference voltages and, secondly, two intermediate reference voltages located in the middle of the half-intervals defined by the three k-1 order main reference voltages, these five reference voltages being used to define three voltage intervals of a width equal to one of the k-1 order half-intervals, PA1 decision means to determine which of the five reference voltages are the three voltages that mutually define an interval with a width equal to a k-1 order half-interval and that most closely surround the input voltage Vin to be converted, the reference voltages thus selected being three k order main reference voltages, PA1 and means for the selection, from the five pairs of interpolation signals, of the three pairs such that the signals of one pair are equal when the voltage Vin is equal to one of the k order main reference voltages. PA1 there are applied, to the input of a k order interpolation circuit, three pairs of analog signals coming from three outputs of the preceding k-1 order interpolation circuit, the signals of a pair having equal values when the voltage Vin is equal to one of there k-1 order main reference voltages each associated with a respective pair, these three voltages mutually defining an interval formed by two k-1 order voltage half-intervals, PA1 there are produced, from these three pairs of signals, P=2.sup.p +1 pairs of interpolation signals (p&gt;1, P&gt;3), each pair comprising two interpolation signals that vary symmetrically and monotonically as a function of the voltage Vin, the signals of a pair being equal when the voltage Vin is equal to a reference voltage associated with this pair, the P reference voltages associated with the P pairs being substantially, firstly, the three k-1 order main reference voltages and, secondly, at least two intermediate voltages located in the middle of the half-intervals defined by the three k-1 order main reference voltages, these P reference voltages enabling the definition of 2.sup.p -1 voltage intervals with a width equal to 1/2.sup.p-1 interval corresponding to the k-1 order, PA1 an operation is carried out to determine, as a function of the levels of the three pairs of input signals, that voltage interval, of the 2.sup.p -1 intervals, that most closely surrounds the input voltage Vin, this interval being formed by two half-intervals demarcated by three out of P reference voltages, these three voltages being called k order reference voltages, PA1 a selection is made, among the P pairs, of the three pairs associated with the three k order reference voltages, and these three pairs are applied to the output of the k order interpolation circuit. PA1 three pairs of inputs receiving, as input signals, three pairs of output signals from a preceding interpolation circuit, the signals of a pair having equal values when the voltage Vin is equal to one of the three k-1 order main reference voltages each associated with a respective pair, these three voltages mutually defining an interval consisting of two k-1 order voltage half-intervals, PA1 means for the setting up, on the basis of the input signals, of P=2.sup.p +1 pairs of interpolation signals (p&gt;1, P&gt;3), each pair comprising two interpolation signals that vary symmetrically and monotonically as a function of the voltage Vin, the signals of one pair being equal when the voltage Vin is equal to a reference voltage associated with this pair, the P reference voltages associated with the P pairs being substantially, firstly, the three k-1 order main reference voltages and, secondly, (P-3) intermediate reference voltages, the P reference voltages enabling the definition of 2.sup.p -1 voltage intervals with a width equal to 1/2.sup.p-1 interval corresponding to the k-1 order, PA1 decision means for the determining, as a function of the levels of the three pairs of input signals, of that voltage interval, among the 2.sup.p -1 intervals, that most closely surrounds the input voltage Vin, this interval consisting of two half-intervals demarcated by three out of P reference voltages, these three voltages being called k order reference voltages, PA1 and means for the selection, from among the P pairs, of the three pairs associated with the three k order reference voltages, to apply them to the output of the k order interpolation circuit.
The qualities of an analog-digital converter result from a compromise between the above parameters, and an aim of the present invention is to improve this compromise.
2. Description of the Prior Art
The known analog to digital converter structures include:
Among the combined converters, several approaches have already been proposed.
In one approach, the coarse converter is a flash converter that gives P bits which are the most significant bits. This value is reconverted into an analog signal by a P bit digital to analog converter. The difference between the analog signal Vin and this reconverted value, also called a remainder or residue, is converted by a fine converter which determines the least significant bits of the conversion. There is a gain in power consumption and in the amount of space required as compared with the flash converter, but the digital to analog conversion takes time and requires a very precise control looping of the gains of the different parts of the circuit (namely the analog-digital converter and the digital-analog converter).
In another approach, the coarse converter is a so-called "parallel sub-range selection" circuit. It consists of a circuit for the selection of a group (or range) of three adjacent reference voltages from a number (or range) of reference voltages greater than three.
This circuit is capable of comparing the input signal Vin with the different reference voltages and then selecting a group of three adjacent main reference voltages such that Vin ranges between these reference voltages, and of making the necessary connections between these three reference voltages, three differential amplifiers and a fine converter circuit.
The coarse converter (by means of a flash converter) gives a digital value indicating the triplet of reference values between which Vin is located.
There is thus obtained an assessment of the adjacent reference range that is as close as possible to Vin. A structure of this type has already been described in the patent application FR-A-2 699 025.
Within this main reference range, a more precise encoding of Vin will then be done by the generation of new intermediate and equidistant reference values. There are several existing methods, but in any case the number of intermediate references must be doubled whenever it is sought to increase the fine encoding precision by a factor of two (namely 1 bit).
These intermediate reference values are generated by so-called "interpolation" circuits.
These interpolations circuits may be parallel or series interpolation circuits.
In parallel interpolation circuits, the number of elements (resistor, amplifier, etc.) implemented increases as the number of intermediate reference values, namely it increases by a factor of two whenever the fine encoding precision increases by 1 bit. For N bits, we therefore have 2.sup.N elements. Hence limits are soon encountered in terms of space requirement and consumption.
By contrast, in the series interpolation circuits, to obtain N information bits, only N elements are necessary.
Hence, as compared with the parallel interpolation, there is a considerable gain in compactness and consumption.
Architectures of this kind have been described in the U.S. Pat. No. 5,126,742 and FR-A-2 699 025.
In these circuits, the number of intermediate references generated increases by a factor of two at output of each interpolation circuit. These circuits all have identical structures and are designed to be cascade-connected.
The signals are periodical functions of the input analog voltage Vin, having a sinusoidal shape. These new signals pass through zero not only when Vin is equal to the main reference voltages but also for intermediate reference voltages located in the middle of the interval between two adjacent main reference voltages.
The signals therefore make it possible to supply an information bit that is additional to the most significant bits obtained by the coarse converter. Signals thus obtained at output of a series interpolation circuit (or stage) are applied to the next stage, which is identical and has the same function as the preceding one (the creation of "period" signals that are again doubled).
The next stage again gives a supplementary bit for the value of Vin.
Continuing in this way, several stages can be cascade-connected to obtain the successive least significant bits of the conversion (it must be noted that these "folded" sinusoidal signals consist of loci of static points as a function of the static values of Vin and are not a priori a function of time).
However, there is a major drawback inherent in the circuits that carry out the folding: by structure, the use of folded signals implies the use of highly nonlinear elements and this is a characteristic that goes against the production of precise intermediate voltages.
The new intermediate voltage values therefore are not equidistant and the precision of the quantification of Vin is therefore diminished.
Now, whatever the interpolation method used for the fine conversion, the intermediate references generated between the main references should be as equidistant as possible.
Any imprecision with respect to this parameter will be expressed by a limitation in the precision of the fine encoding of Vin. Now, while the serial interpolation circuits have effectively resolved the problems of space requirement and consumption as compared with parallel interpolation circuits, it is with great difficulty that they permit encoding precision of over 10 bits.
This arises directly from the non-linearity of the folding method used.